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rt8204a 1 ds8204a-05 april 2011 www.richtek.com single synchronous buck with ldo controller applications z notebook computers z cpu core supply z chipset/ram supply as low as 0.75v general description the rt8204a pwm controller provides the high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, i/o, and chipset ram supplies in notebook computers. the constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ? instant-on ? response to load transients while maintaining a relatively constant switching frequency. the rt8204a achieves high efficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode pwms. efficiency is further enhanced by its ability to drive very large synchronous rectifier mosfets. the buck conversion allows this device to directly step down high voltage batteries for the highest possible efficiency. the rt8204a is intended for cpu core, chipset, dram, or other low voltage supplies as low as 0.75v. a built-in ldo controller can drive an external n-mosfet to provide a second output voltage from pwm output or other power source. the rt8204a can provide adjustable voltage down to 0.75v and maximum output voltage is depended on the selected mosfet. the internal 0.75v reference voltage with 1.5% accuracy provides tight regulation for the output voltage. the independent enable control, open drain power good indicator, under-voltage protection and soft start make rt8204a to power the system friendly. the rt8204a is available in wqfn-16l 3x3 package. features z z z z z pwm controller ` ` ` ` ` ultra-high efficiency ` ` ` ` ` resistor programmable current limit by low side r ds(on) sense (lossless limit) or sense resistor (high accuracy) ` ` ` ` ` quick load step response within 100ns ` ` ` ` ` 1% v out accuracy over line and load ` ` ` ` ` adjustable 0.75v to 3.3v output range ` ` ` ` ` 3v to 26v battery input range ` ` ` ` ` resistor programmable frequency ` ` ` ` ` over/under voltage protection ` ` ` ` ` 2 steps current limit during soft-start ` ` ` ` ` drives large synchronous-rectifier fets ` ` ` ` ` power good indicator z z z z z ldo controller ` ` ` ` ` 1.5% accuracy over line and load ` ` ` ` ` adjustabe output voltage down to 0.75v ` ` ` ` ` independent enable and power good indicator ` ` ` ` ` drive n-mosfets within rail to rail controller voltage ` ` ` ` ` mlcc and poscap stable z z z z z rohs compliant and 100% lead (pb)-free marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. rt8204a package type qw : wqfn-16l 3x3 (w-type) lead plating system p : pb free g : green (halogen free and pb free)
rt8204a 2 ds8204a-05 april 2011 www.richtek.com typical application circuit pin configurations (top view) wqfn-16l 3x3 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 pgood fb vout vdd ugate phase vddp oc lpgood ldrv lfb lgate ton en/dem boot len gnd 17 1 5 1 2 1 1 8 3 v d d p e n / d e m u g a t e f b r t 8 2 0 4 a l g a t e 9 1 3 b o o t p h a s e v o u t 1 l 1 v i n v d d 2 p g o o d 4 p g o o d g n d e x p o s e d p a d ( 1 7 ) t o n 1 6 v d d p 5 v c 1 4 . 7 f r 2 1 0 0 k r 1 1 0 c 2 1 f c c m / d e m d 1 b a t 2 5 4 3 v t o 2 6 v r 4 1 m r 5 2 . 2 r 6 0 r 7 1 0 k c 3 0 . 1 f c 4 1 0 f q 1 a o 4 7 0 4 q 2 a o 4 7 0 4 2 . 4 h r 8 c 5 r 9 1 2 k c 8 c 9 2 2 0 f c 1 2 v o u t 1 1 . 2 v 1 0 o c r 1 2 1 2 k r 1 3 3 0 k c 1 1 1 0 f c 1 0 2 2 0 f v o u t 2 1 . 0 5 v ldrv lfb len 1 4 l d o e n a b l e lpgood l d o p g o o d v d d p r 1 0 2 0 k r 1 1 c 7 3 3 n f q 3 a o 4 4 0 4 r 3 1 0 0 k 7 6 5 c 6 c 1 3 0 . 1 f
rt8204a 3 ds8204a-05 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 vout vout sense input. connect to the output of pwm converter. vout is an input of the pwm controller. 2 vdd analog supply voltage input for the internal analog integrated circuit. bypass to gnd with a 1 f ceramic capacitor. 3 fb vout feedback input. connect fb to a resistor voltage divider from vout to gnd to adjust the output from 0.75v to 3.3v. 4 pgood power good signal open-drain output of pwm converter. this pin will be pulled high when the output voltage is within the target range. 5 lpgood power good signal open-drain output of ldo regulator. this pin will be pulled high when the output voltage is within the target range. 6 lfb ldo feedback input. connect lfb to a resistor voltage divider from vout to gnd to adjust the output greater than 0.75v. 7 ldrv drive signal for the ldo?s path mosfet. 8 lgate low side n-mosfet gate-drive output for pwm. this pin swings between gnd and vddp. 9 vddp vddp is the gate driver supply for the external mosfets. bypass to gnd with a 1 f ceramic capacitor. 10 oc pwm current limit setting and sense. connect a resistor between oc to phase for current limit setting. 11 phase inductor connection. this pin is not only the zero-current-sense input for the pwm converter, but also the ugate high side gate driver return. 12 ugate high side n-mosfet floating gate-driver output for the pwm converter. this pin swings between phase and boot. 13 boot boost capacitor connection for pwm converter. connect an external ceramic capacitor to phase and an external diode to vddp. 14 len ldo enable input with internal pull low resistor. ldo is enabled if len is greater than the on level and disabled if len is less than the off level. 15 en/dem pwm enable and operation mode selection input. connect to vdd for diode emulation mode, connect to gnd for shutdown mode and floating the pin for ccm mode. 16 ton vin sense input. connect to vin through a resistor. ton is an input of the pwm controller. 17 (exposed pad) gnd analog ground and power ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
rt8204a 4 ds8204a-05 april 2011 www.richtek.com function block diagram pwm controller ldo controller r q s min. t off qtrig 1-shot + - + - comp gm + - ss (internal) 0.75v v ref s1 q latch s1 q latch + - ov + - uv 115% v ref 70% v ref + - 90% v ref ss timer thermal shutdown diode emulation drv drv + - 20a on-time compute 1-shot oc fb vout vdd ugate phase vddp pgood pgnd gnd lgate ton en/dem boot trig + - + - + - 50% v ref 90% v ref 0.75v v ref ss ramp x1 ss lpgood ldrv lfb len
rt8204a 5 ds8204a-05 april 2011 www.richtek.com absolute maximum ratings (note 1) z input voltage, to n to gnd ---------------------------------------------------------------------------------------------- ? 0.3v to 32v z boot to gnd -------------------------------------------------------------------------------------------------------------- ? 0.3v to 38v z phase to boot ---------------------------------------------------------------------------------------------------------- ? 6v to 0.3v z phase to gnd dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 32v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 8v to 38v z vdd, vddp, vout, en/dem, len, lfb, fb, pgood, lpgood, ldrv to gnd ----------------------- ? 0.3v to 6v z ugate to phase dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 5v to 7.5v z oc to gnd ------------------------------------------------------------------------------------------------------------------ ? 0.3v to 28v z lgate to gnd dc ----------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v <20ns ------------------------------------------------------------------------------------------------------------------------ ? 2.5v to 7.5v z power dissipation, p d @ t a = 25 c wqfn-16l 3x3 ------------------------------------------------------------------------------------------------------------ 1.471w z package thermal resistance (note 2) wqfn-16l 3x3, ja ------------------------------------------------------------------------------------------------------- 68 c/w wqfn-16l 3x3, jc ------------------------------------------------------------------------------------------------------ 7.5c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (v dd = v ddp = 5v, v in = 15v, v out = 1.25v, en/dem = v dd , r ton = 1m , t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit pwm controller quiescent s uppl y c urrent vdd + vddp, fb = 0.8v, forced above the regulation point -- -- 1250 a ton operating current r ton = 1m -- 15 -- a vdd + vddp -- 1 10 ton -- 1 -- shutdown current i shd n en/dem = 0v ? 10 ? 1 -- a to be continued recommended operating conditions (note 4) z input voltage, v in ---------------------------------------------------------------------------------------------------------- 3v to 26v z supply voltage, v dd , v ddp ---------------------------------------------------------------------------------------------- 4.5v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
rt8204a 6 ds8204a-05 april 2011 www.richtek.com parameter symbol test conditions min typ max unit fb reference voltage v fb v dd = 4.5 to 5.5v 0.742 0.75 0.758 v fb input bias current fb = 0.75v ? 1 0.1 1 a output voltage range 0.75 -- 3.3 v on-time v in = 15v, v out = 1.25v, r ton = 1m 267 334 401 ns minimum off-time 250 400 550 ns v out shutdown discharge resistance en/dem = gnd -- 20 -- current sensing i li m source current lgate = high 18 20 22 a current comparator offset gnd to oc ? 10 -- 10 mv zero crossing threshold phase to gnd, en/dem = 5v ? 10 -- 5 mv fault protection gnd to phase, r ilim = 2.5k 35 50 65 current limit sense voltage v rilim gnd to phase, r ilim = 10k 170 200 230 mv output uv threshold 60 70 80 % ovp threshold with respect to error comparator threshold 10 15 20 % ov fault delay fb forced above ov threshold -- 20 -- s vdd uvlo threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.3 4.5 v soft-start ramp time from en high to internal v ref reach 0.71v (0 ? 95%) -- 1.35 -- ms uv blank time from en signal going high -- 3.1 -- ms thermal shutdown -- 155 -- c thermal shutdown hysteresis -- 10 -- c driver on-resistance ugate driver pull up boot to phase forced to 5v -- 1.5 5 ugate driver sink r ugatesk boot to phase forced to 5v -- 1.5 5 lgate driver pull up lgate, high state (source) -- 1.5 5 lgate driver pull down lgate, low state (sink) -- 0.6 2.5 ugate driver source/sink current ugate forced to 2.5v, boot to phase forced to 5v -- 1 -- a lgate driver source current lgate forced to 2.5v -- 1 -- a lgate driver sink current lgate forced to 2.5v -- 3 -- a lgate rising (phase = 1.5v) -- 30 -- dead time ugate rising -- 30 -- ns logic i/o logic input low voltage en/dem low -- -- 0.8 v en/dem high 2.9 -- -- logic input high voltage en/dem float -- 2 -- v en/dem = v dd -- 1 5 logic input current en/dem = 0 ? 5 ? 1 -- a to be continued
rt8204a 7 ds8204a-05 april 2011 www.richtek.com parameter symbol test conditions min typ max unit pgood (upper side threshold decide by ov threshold) trip threshold (falling) measured at fb with respect to reference, no load. hysteresis = 3% ? 13 ? 10 ? 7 % fault propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s output low voltage i sin k = 1ma -- -- 0.4 v leakage current high state, forced to 5v -- -- 1 a ldo controller quiescent current i q pwm off, ldo on, i out = 0ma -- -- 400 a shut-down current i shdn -- -- 5 a input voltage uvlo 4.1 -- 4.5 v len logic high voltage v len_h 2 -- -- v len logic low voltage v len_l -- -- 0.8 v len input current i len len = 5v (internal pull low) -- -- 10 a lfb reference voltage v lfb 0.739 0.75 0.761 v lfb input current i lfb ? 1 -- 1 a sourcing i ldrv_sr v lfb = 0. 72v 1.4 2 -- ldrv output current sinking i ldrv_sk v lfb = 0. 78v 1.4 2 -- ma output uvp threshold measured at lfb pin 40 50 60 % uvp propagation delay -- 2.5 -- s pgood threshold (fa lling) measured at lfb pin 87 90 93 % pgood propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s pgood low voltage i sin k = 1ma -- -- 0.4 v pgood leakage current high state, forced to 5v -- -- 1 a thermal shutdown -- 155 -- c thermal shutdown hysteresis -- 10 -- c note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. the case point of jc is on the expose pad for the wqfn package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt8204a 8 ds8204a-05 april 2011 www.richtek.com typical operating characteristics vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem pwm v in = 8v switching frequency vs. output current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) v in = 8v dem pwm vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 12v dem pwm switching frequency vs. output current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) v in = 12v dem pwm vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v in = 24v dem pwm switching frequency vs. output current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 output current (a) switching frequency (khz) v in = 24v dem pwm
rt8204a 9 ds8204a-05 april 2011 www.richtek.com ugate (20v/div) shutdown current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown current (ua) en = gnd, no load standby current vs. input voltage 280 290 300 310 320 330 340 350 360 370 380 390 400 7 9 11 13 15 17 19 21 23 25 input voltage (v) standby current (ua) en = 5v, no load ldo output voltage vs. output current 1.0500 1.0505 1.0510 1.0515 1.0520 1.0525 1.0530 1.0535 1.0540 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output current (a) output voltage (v) v in = 1.25v v in = 12v, en = floating, no load power on from en time (800 s/div) en/dem (2v/div) phase (10v/div) v out (1v/div) pgood (5v/div) pwm-mode v in = 12v, en = 5v, no load power on from en time (800 s/div) en/dem (5v/div) phase (10v/div) v out (1v/div) pgood (5v/div) dem-mode v in = 12v, en = floating, no load power off from en time (4ms/div) en/dem (2v/div) v out (1v/div) lgate (5v/div)
rt8204a 10 ds8204a-05 april 2011 www.richtek.com vout1 load transient response time (10 s/div) i load (5a/div) v out_ac (50mv/div) lgate (5v/div) v in = 12v, en = floating, i out1 = 0a to 6a ugate (20v/div) ovp time (40 s/div) v out (1v/div) lgate (5v/div) ugate (10v/div) v in = 12v, en = 5v, no load uvp time (20 s/div) v out (1v/div) lgate (5v/div) ugate (20v/div) v in = 12v, en = floating, no load inductor current (10a/div) power on in short condition time (800 s/div) i load (10a/div) v out (1v/div) lgate (5v/div) v in = 12v, en = floating, v out1 short ugate (20v/div) ldo load transient response time (100 s/div) i load (5a/div) v out_ac-coupled (100mv/div) ldri (2v/div) v in = 1.25v, c out = 10 f x 2, i out2 = 0.1a to 4a v in = 1.25v, c out = 10 f x 2, no load ldo power on from len time (100 s/div) len (5v/div) ldri (2v/div) v out (1v/div) lpgood (5v/div)
rt8204a 11 ds8204a-05 april 2011 www.richtek.com v in = 1.25v, v out2 short, c out = 10 f x 2 ldo short-circuit protection time (100 s/div) i load (20a/div) ldri (5v/div) v out (1v/div) lpgood (5v/div)
rt8204a 12 ds8204a-05 april 2011 www.richtek.com application information the rt8204a pwm controller provides the high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, i/o, and chipset ram supplies in notebook computers. richtek's mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load transient timing problems of fixed-frequency current mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant- off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a single output application. pwm operation the mach response tm , drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the function diagrams of rt8204a, the synchronous high side mosfet is turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet is turned off. the pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (400ns typ.). on-time control (ton) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to v out , thereby making the on-time of the high side switch directly proportional to output voltage and inversely proportional to input voltage. the implementation results in a nearly constant switching frequency without the need of a clock generator. t on = 3.85p x r ton x v out / (v in ? 0.5) and then the switching frequency is : frequency = v out / (v in x t on ) r ton is a resistor connected from the input supply (v in ) to the ton pin. mode selection (en/dem) operation the en/dem pin enables the supply. when en/dem is tied to vdd, the controller is enabled and operates in diode-emulation mode. when the en/dem pin is floating, the rt8204a will operate in forced-ccm mode. diode-emulation mode (en/dem = high) in diode-emulation mode, rt8204a automatically reduces switching frequency at light load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly without increasing the v out ripple or load regulation. as the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial of negative current when the inductor freewheeling current reach negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level than requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. the transition load point to the light-load operation can be calculated as follows (figure 1) : in out load on (v v ) i t 2l ? ? i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2 figure 1. boundary condition of ccm/dem
rt8204a 13 ds8204a-05 april 2011 www.richtek.com the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-off in dem noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degrades load-transient response (especially at low input-voltage levels). forced-ccm mode (en/dem = floating) the low noise, forced-ccm mode (en/dem = floating) disables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low side gate- drive waveform to become the complement of the high- side gate-drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio v out /v in . the benefit of forced-ccm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be up to 10ma to 40ma, depending on the external mosfets. current limit setting (ocp) the rt8204a has cycle-by-cycle current limiting control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current-sense signal at oc is above the current limit threshold, the pwm is not allowed to initiate a new cycle (figure 2). i l t 0 i l, peak i lim i load figure 2. valley current-limit current sensing of the rt8204a can be accomplished in two ways. users can either use a current sense resistor or the on-state of the low-side mosfet (r ds(on) ). for resistor sensing, a sense resistor is placed between the source of low-side mosfet and pgnd (figure 3(a)). r ds(on) sensing is more efficient and less expensive (figure 3(b)). there is a compromise between current limit accuracy and sense resistor power dissipation. r ilim lgate phase oc r ilim lgate phase oc figure 3. current-sense methods (a) (b) in both cases, the r ilim resistor between the oc pin and phase pin sets the over current threshold. this resistor r ilim is connected to a 20 a current source within the rt8204a which is turned on when the low side mosfet turns on. when the voltage drop across the sense resistor or low-side mosfet equals the voltage across the r ilim resistor, positive current limit will be activated. the high side mosfet will not be turned on until the voltage drop across the sense element (resistor or mosfet) falls below the voltage across the r ilim resistor. choose a current limit resistor by following equation : r ilim = i limit x r sense / 20 a carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signal seen by oc and pgnd. mount the ic close to the low-side mosfet and sense resistor with short, direct traces, making a kelvin sense connection to the sense resistor.
rt8204a 14 ds8204a-05 april 2011 www.richtek.com mosfet gate driver (ugate, lgate) the high side driver is designed to drive high current, low r ds(on) n-mosfets. when configured as a floating driver, 5v bias voltage is delivered from vddp supply. the average drive current is proportional to the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between boot and phase pins. a dead time to prevent shoot through is internally generated between high side mosfet off to low side mosfet on, and low side mosfet off to high side mosfet on. the low side driver is designed to drive high current, low r ds(on) n-mosfets. the internal pull-down transistor that drives lgate low is robust, with a 0.6 typical on- resistance. a 5v bias voltage is delivered form vddp supply. the instantaneous drive current is supplied by the flying capacitor between vddp and pgnd. for high current applications, some combinations of high and low side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with boot, which increases the turn-on time of the high-side mosfet without degrading the turn-off time (figure 4). boot ugate phase r +5v v in figure 4. the ugate rise time reduction power-good output (pgood) the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 15% above or 10% below its set voltage, the pgood gets pulled low. it is held low until the output voltage returns to within these tolerances once more. in soft start, the pgood is actively held low and is allowed to be pulled high until soft start is over and the output reaches 93% of its set voltage. there is a 2.5 s delay built into the pgood circuitry to prevent false transition. por, uvlo and soft-start power-on reset (por) occurs when vdd rises above to approximately 4.3v, the rt8204a will reset the fault latch and prepare the pwm for operation. if the vdd is below 4.1v (min) , the vdd undervoltage-lockout (uvlo) circuitry inhibits switching by keeping ugate and lgate low. a built-in soft-start is used to prevent the surge current from power supply input after en/dem is enabled. it clamps the ramping of internal reference voltage which is compared with the fb signal. the typical soft-start duration is 1.35ms. furthermore, the maximum allowed current limit is segment in 2 steps during 1.35ms period. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when the output voltage exceeds 15% of the its setting voltage threshold, the over voltage protection is triggered and the low side mosfet is latched on. this activates the low side mosfet to discharge the output capacitor. the rt8204a is latched once ovp is triggered and can only be released by vdd or en/dem power on reset. there is a 20 s delay built into the over voltage protection circuit to prevent false transitions. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 70% of its set voltage threshold, the under voltage protection is triggered and then both ugate and lgate gate drivers are forced low. in order to remove the residual charge on the output capacitor during the under voltage period, if the phase is greater than 1v, the lgate is forced high until phase is lower than 1v. there is 2.5 s delay built into the under voltage protection circuit to prevent false transitions. during the soft-start, the uvp will be blanked around 3.1ms. output voltage setting (fb) the output voltage can be adjusted from 0.75v to 3.3v by setting the feedback resistor r1 and r2 (figure 5). choose r2 to be approximately 10k , and solve for r1 using the equation :
rt8204a 15 ds8204a-05 april 2011 www.richtek.com out fb r1 v = v 1 r2 ?? ?? + ?? ?? ?? ?? where v fb is 0.75v. note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, v fb , should be approximately 15mv at minimum v bat , and worst case no smaller than 10mv. if v ripple at minimum v bat is less than 15mv, the above component values should be revisited in order to improve this. quite often a small capacitor, c1, is required in parallel with the top feedback resistor, r1, in order to ensure that v fb is large enough. the value of c1 can be calculated as follows, where r2 is the bottom feedback resistor. firstly calculating the value of z1 required : () ripple_vbat(min) r2 z1 = v 0.015 0.015 ? secondly calculating the value of c1 required to achieve this : ( ) sw_vbat(min) 11 z1 r1 c1 = f 2f ? finally using the equation as follows to verify the value of v fb : fb_vbat(min) ripple_vbat(min) sw_vbat(min) v = v r2 v 1 r2+ 1 2f c1 r1 ?? ?? ?? ?? ?? ?? + ?? where v ripple_vbat(min) is the output ripple voltage in minimum v bat ; f sw_vbat(min) is the switching frequency in minimum v bat ; v fb_vbat(min) is the ripple voltage into fb pin in minimum v bat . phase boot r1 r2 v out v in ugate vout fb gnd c1 c2 z1 figure 5. setting the output voltage for application that output voltage is higher than 3.3v, user can also use a voltage divider to keep vout pin voltage within 0.75v to 2.8v as shown in figure 6. for this case, t on can be determined as below : ton out_fb ton on in ton out_fb ton on in rv if r < 2m then t = 3.85p v0.5 r v if r 2m then t = 3.55p v0.4 ? ? ? ? where r ton is t on set resistor and the v out_fb is the output signal of resistor divider. since the switching frequency is out s in on v f = vt for a given switching frequency, we can obtain the r ton as below ton out out ton in out_fb s ton out out ton in out_fb s if r < 2m then v0.5v 1 r = v v f 3.85p if r 2m then v0.4v 1 r = v v f 3.55p ? ? ? figure 6. output voltage setting for v out > 3.3v application phase boot r1 r2 v out v in ugate vout fb gnd c2 vin r ton r3 r4 v out_fb output inductor selection the switching frequency (on-time) and operating point (% ripple or l ir ) determine the inductor value as follows : on in out ir load(max) t(v - v) l = li
rt8204a 16 ds8204a-05 april 2011 www.richtek.com find a low pass inductor having the lowest possible dc resistance that fits in the allowed dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough and not to saturate at the peak inductor current (i peak ) : i peak = i load(max) + [(l ir / 2) x i load(max) ] output capacitor selection the output filter capacitor must have esr low enough to meet output ripple and load transient requirement, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the ovp circuit. for cpu core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance : p-p load(max) v esr i in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain at an acceptable level of output voltage ripple : p-p ir load(max) v esr li sw esr out f 1 f = 2 esr c 4 organic semiconductor capacitors or specially polymer capacitors are recommended. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high esr zero frequency and cause erratic and unstable operation. however, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting v out or fb divider close to the inductor. there are two related but distinct ways including double- pulsing and feedback loop instability to identify the unstable operation. double-pulsing occurs due to noise on the output or because the esr is too low that there is not enough voltage ramp in the output voltage signal. the ? fools ? the error comparator into triggering a new cycle immediately after 400ns minimum off-time period has expired. double- pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with ac probe. do not allow more than one ringing cycle after the initial step-response under- or over-shoot. ldo normal operation the rt8204a ldo controls an n-mosfet to produce a tightly regulated output voltage from higher supply voltage. it takes 5v power supply for controller and draws maximally 400 a while operating. the feedback voltage is regulated to compare with the internal 0.75v reference voltage. to set the output voltage, feedback the conjunction of a resistor voltage divider from output node to ground for the lfb pin. depending upon the input voltage used for the device, the ldrv pin can be pulled up near to vdd. thus the device can be used to regulate a large range of output voltage by careful selection of the external mosfets. a built-in active high enable control (len pin) is used to turn the rt8204a ldo on. if this pin is pulled low, the ldrv pin is pulled low, turning off the n-mosfet. if this pin is pulled higher than 2v, the ldrv pin is enabled.
rt8204a 17 ds8204a-05 april 2011 www.richtek.com the rt8204a ldo contains a power good output pin (lpgood pin) which is an open drain output that will be pulled low if the output is below the power good threshold (typically 90% of the programmed output voltage, or 93% at the start up). the power good detection is active if the rt8204a ldo is enabled. the rt8204a ldo also includes a under voltage protection circuit that monitors the output voltage. if the output voltage drops below 50% (typical) of the nominal value, as would occur during over current or short condition, the rt8204a ldo will pull the ldrv pin low and latch off. the rt8204a ldo is latched once the uvp is triggered and can only be relieved by the vdd or len power-on reset. ldo driver and stability design the drive output (ldrv pin) is sink/source capable. the sink current is typically 2ma while the source current is typically 2ma in normal operation. the drive output is also used for stabilizing the loop of the system using different type of the output capacitor. the components listed in the table below should be used. table 1. ldo configuration and compensation ldo configuration compensator input voltage output voltage c7 c8 r11 1.25v 1.05v 33nf 39pf 82 1.5v 1.05v 33nf 47pf 43 1.5v 1.25v 33nf 47pf 30 1.8v 1.5v 33nf 39pf 100 note: test condition is output capacitor 220 f(esr : 9 to 25m ) or 100 f(esr : 9 to 15m ) + mlcc 10 foutput current is from 0.1a to 5a ldo output under voltage protection(uvp) the rt8204a ldo has output under voltage protection that looks at the output to see if it is : (a) the ldo output voltage is less than 50% (typical) of its nominal value and (b) the v drv is within 900mv (typical) of its maximum. this provides inherent immunity to under voltage shut down at start up since v drv has a slow rate of rising at this moment. if both of these criteria are met, the output will be shut down by means of the v drv pulled to ground immediately. if the vddp input is coming prior to the ldo_vin, it could accidentally meet the uvp fault protection. to avoid entering uvp latch off, using enable control (len pin) to turn the system on whenever all power supplies are ready. please see the power sequencing example as below (figure 7). figure 7. power supply sequencing ldo output voltage setting the lfb pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistor r3 and r4 (figure 8). the following equation is for adjusting the output voltage. out lfb r3 v = v 1 r4 ?? ?? + ?? ?? ?? ?? where v lfb is 0.75v (typ.). rt8204a supply comes up be fore mosfet drain supply vddp ldo_vin len vth(uv) = 0.88v vth(len) occurs after vth(uv) is reached vth(len) = 2v mosfet drain supply comes up before rt8204a supply len vddp vth(uv) = 0.88v ldo_vin vth(len) = 2v vth(len) occurs after vth(uv) is reached len rising with vddp shown
rt8204a 18 ds8204a-05 april 2011 www.richtek.com ldrv lfb ldo_vin ldo_vout r3 r4 figure 8. ldo output voltage setting ldo output capacitor selection low esr capacitors such as sanyo poscaps or panasonic sp-caps are recommended for bulk capacitance, and ceramic bypass capacitors are recommended for decoupling high frequency transients. ldo input capacitor selection low esr capacitors such as sanyo poscaps or panasonic sp-caps are recommended for the input capacitors to provide better load transient response. if the ldo input is connected from the output of buck converter (v out1 ), a 0.1 f ceramic capacitor will sufficient. ldo mosfet selection low threshold n-mosfets are required. for the device to work under all operating conditions, a maximum r ds(on) must be met to ensure that the output will not go into dropout : in(min) out(max) ds(on)(max) out(peak) vv r = i ? layout considerations layout is very important in high frequency switching converter design. if the layout is designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. certain points must be considered before starting a layout for the rt8204a. ` connect an rc low pass filter from vddp to vdd, 1 f and 10 are recommended. place the filter capacitor close to the ic. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. ` all sensitive analog traces and components such as vout, fb, gnd, en/dem, pgood, oc, vdd, and ton should be placed away from high voltage switching nodes such as phase, lgate, ugate, or boot nodes to avoid coupling. use internal layers as ground planes and shield the feedback trace from power traces and components. ` current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` power sections should connect directly to ground planes using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. note that r ds(on) must be met for operating temperature range at the minimum v gs condition. power consumptions of the n-mosfets should be taken into consideration for the selection of various package types.
rt8204a 19 ds8204a-05 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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